1. Field of the Invention
This invention relates generally to processor-based systems, and, more particularly, to arbitrating master-slave transactions in processor-based systems.
2. Description of the Related Art
Businesses may use processor-based systems to simultaneously perform a wide variety of tasks. These tasks may include, but are not limited to, developing new software, maintaining databases of information related to operations and management, and hosting a web server that may facilitate communications with customers. To handle such a wide range of tasks, businesses may employ a processor-based system in which some or all of the processors may operate in a networked environment.
One example of a processor-based system used in a network-centric environment is a mid-range server system. A single mid-range server system may have a plurality of system boards that may, for example, contain one or more processors and one or more associated memory elements. A mid-range server system may also have a plurality of I/O boards that may support a range of I/O devices such as CD-ROMs, printers, scanners, and the like through one or more I/O cards. For example, one or more I/O boards in the mid-range server system may manage peripheral component interface cards and/or optical cards.
Devices supported by the plurality of system and I/O boards may exchange data. For example, data provided by a scanner may be written to one of the memory elements. Similarly, data that is stored in a memory element may be delivered to a printer. To facilitate the data exchange, the devices supported by the various system and I/O boards in a mid-range server system may be coupled to one or more buses, which may provide a data transfer pathway for the devices supported by the plurality of system and I/O boards in the system.
However, the bus may only support one data transaction between one pair of components at a given time. Thus, each device must request permission from a bus arbiter before the device may be allowed to transmit data along the bus. For example, in master/slave bus architectures, certain devices that are designated as masters may be able to request permission from the bus arbiter, which may determine whether or not a transaction is occurring on the bus. If the bus is not currently being used for a transaction, the bus arbiter may grant permission to the master, which may then send data along the bus to a slave device. The slave device generally includes a buffer to store the data and provide it to one of a plurality of devices that may be coupled to the slave device.
A plurality of master devices may be coupled to the bus and the requests from each master may not always arrive in a predictable order. To reasonably fairly distribute access to the bus among the plurality of master devices, the bus arbiter may implement a distribution algorithm such as a round-robin algorithm. In the round-robin algorithm, each master device may be associated with a position on a circle. When the bus arbiter grants permission to a first requesting master device, a pointer may be rotated to the position corresponding to the first requesting master device. Once the transaction is substantially complete, the bus arbiter may determine which master devices are currently requesting access to the bus. The bus arbiter may then rotate the pointer in a selected direction around the circle until it arrives at a position corresponding to a second requesting master device. The bus arbiter may then grant permission to the second requesting master device.
However, this method may occasionally break down. For example, the buffer of the slave device may become full after processing the first requesting master device's request and the slave device may take several clock cycles to complete emptying its buffer. In that time, the bus arbiter may grant permission to one or more second requesting master devices, which may attempt to send data to the slave. But the slave device may reject the requests from the one or more second requesting master devices. The slave may begin accepting requests once it has emptied its buffer, but by this time the pointer in the bus arbiter may have returned to the original requesting master, bypassing the others. Thus, one master device may repeatedly gain access to the slave device at the expense of other master devices. This may reduce the efficiency of the system and, in some cases, cause the system to crash.